1. Field of the Invention
The present invention relates to control of a memory apparatus including a CPU (Central Processing Unit), a DMAC (Direct Memory Access Controller), and a DRAM (Dynamic Random Access Memory), and to an optical filing system using this memory control.
2. Description of the Related Art
When a processor clock period of a CPU or a DMAC and an operation clock of a DRAM are the same but their phases do not match each other, one of the processor clock and operation clock is removed by one clock to perform phase matching so that a transit point of the processor clock matches that of the DRAM operation clock. Therefore, a circuit design of a memory apparatus can be made easy by designing an output timing of data read out from a DRAM to be matched with a transit point of an operation clock of the DRAM.
As development of CPU techniques has progressed and speed of a CPU processor clock has been increased, however, speed of a DRAM operation clock must be increased (or an access time of a DRAM must be shortened) accordingly. When a DMAC is operated with a low-speed processor clock, even if the output timing of readout data from the DRAM is matched with the transit point of the DRAM operation clock, this output timing does not always coincide with the transit point of the CPU processor clock. As a result, a throughput in data processing of an optical filing system, including the memory apparatus, becomes low.